Semiconductor devices manufactured as integrated circuits may consist of billions of devices, including transistors, diodes, passives, MEMs, and other structures being built in and over a substrate that is typically a silicon wafer, which may undergo multiple microfabrication process steps, including doping, ion implantation, etching, deposition of various materials, and photolithographic patterning. The pin count of very large scale integration (VLSI) circuits has grown steadily, and as the designs of semiconductor devices increase in complexity and diversity, more advanced test systems are needed.
Testing of semiconductor integrated circuits may occur through the simulation of complex ICs, through testing that forms an integral part of post-silicon validation of prototype and/or pre-production ICs, as well as through the testing that forms an integral part of its manufacturing process. Testing throughout post-silicon validation is focused on insuring the IC performs per its various specified functional features and specified performance characteristics. Testing throughout manufacture may include a pre-processing step of testing the wafer during fabrication, which is commonly referred to as Wafer Testing and Electronic Die Sort testing, and which may occur on a lot by lot basis. Product testing of the completed semiconductor devices may also occur on a lot by lot basis, as well as some random sampling testing to determine quality.
Automatic Test Equipment (ATE) is therefore heavily utilized in the semiconductor industry to verify functionality, performance, or find faults before that integrated circuit—the Device Under Test (DUT)—is actually utilized in an electronic end-product. The testing of semiconductors utilizing ATE is known in the art (see e.g., U.S. Pat. No. 5,225,772 to Cheung; U.S. Pat. No. 5,235,271 to Kira; and U.S. Pat. No. 5,737,512 to Proudfoot, with the disclosures of each being incorporated herein by reference). Usage of ATE for testing semiconductors may be accomplished through the use of a “tester” that is coupled to the pins of the DUT, and which operates in accordance with specialized test programs that are prepared for specific device types. Circuits within the tester equipment serve as an interface between the DUT and a computer system that is controlling the tests and testing system. Stimuli signals in the form of digital, analog, or RF are thereby input to the pins of the DUT from the tester using drivers associated with each interface circuit. The interface circuits of the tester similarly receive output signals from the DUT pins which processes & compares the signals actually received from the DUT with an expected response that is stored in the computer system. The ATE for the testing of semiconductor devices may also comprise the use of a DUT loadboard. The loadboard may provide an arranged series of sockets or probes for receiving one or more devices on one side of the board, while printed circuits on the other side may serve for mapping and/or conditioning of the contacts corresponding to the pins of the DUT(s). The loadboard will ordinarily be customized for testing of a specific integrated circuit design type.
In order to perform checks of complex semiconductor devices, the computer systems of such automated testing equipment must generally produce testing steps in a deterministic way and execute those testing steps to achieve reliable evaluations of the specific functionality/performance of the particular device. This imposes limitations, in terms of the hardware design, software design, maintenance costs, etc., whereby operations are inefficient and do not effectively match how the various DUT interfaces are intended to operate. The present invention serves to diversify operability of legacy, fixed architecture instrumentation, whereby operations are effectively matched to the various DUT interfaces. The present invention also serves to seamlessly integrate testing of a DUT between pre-silicon simulation, post-silicon validation, and production test phases whereby, in one embodiment the same software and hardware can be used across all three phases.
The advantages of the present invention are not taught or suggested by the prior art. For example, U.S. Patent Application No. 2010-0052754 by Mizuno teaches a circuit to cost effectively expand the number of a legacy fixed architecture digital channels on a low pin count test system using a fan out/fan in approach. The instrument is still a legacy fixed instrument architecture that is cycle & time set based, with no native links to the design environment.
U.S. Pat. No. 7,944,225 Kemmerling: this is another circuit to cost effectively expand the number of a legacy fixed architecture digital channels on a low pin count test system using a fan out/fan in approach. The instrument is still a legacy fixed instrument architecture that is cycle & time set based with no native links to the design environment.
U.S. Pat. No. 5,225,772 to Cheung teaches an enhancement to a legacy fixed architecture digital instrument to provide more per-pin flexibility. The instrument is still a legacy fixed instrument architecture that is cycle & time set based with no native links to the design environment.
U.S. Pat. No. 5,235,271 to Kira teaches a method to use data collected from wafer sort testing to optimize the test list for final (package) testing by switching off tests at final that are statistically in control at wafer test. This is a methodology that is independent of the tester architecture.
U.S. Pat. No. 5,737,512 to Proudfoot teaches an enhancement to a legacy fixed architecture digital instrument to provide faster loading of the cycle based data into the instrument memory from the external tester computer. The instrument is still a legacy fixed instrument architecture that is cycle & time set based with no native links to the design environment.
U.S. Pat. No. 7,924,043 to Schroth teaches an enhancement to a legacy fixed architecture digital instrument to provide signal pre-compensation to account for distortions in the signal path to the device. The instrument is still a legacy fixed instrument architecture that is cycle & time set based with no native links to the design environment.
U.S. Pat. No. 7,428,680 to Mukherjee teaches a circuit that is incorporated into the IC itself specifically for use in testing the internal memories in the IC using different algorithms. This internal built in test circuit (BIST) is unrelated to the external tester architecture.
U.S. Pat. No. 7,620,862 to Lai teaches an enhancement to a legacy fixed architecture digital instrument to multiply the data rate of the tester and effectively create higher speed patterns at the device pin. The tester instrument is nonetheless a legacy fixed instrument architecture that is cycle & time set based, with no native links to the design environment.
U.S. Patent Application No. 2004-0162694 by Ricca teaches a highly specific enhancement to a fixed architecture waveform synthesizer/digitizer which can be set to several specific modes (LF synth, HF synth, LF dig, HF dig). The implementation is quite specific. They do load the FPGA in one of 2 modes—synth or dig. It is not reconfigurable to the extent proposed herein—which may be considered as 4 fixed architecture instruments on one card. In Ricca, here is also no native link to the design environment claimed.
U.S. Pat. No. 8,065,663 to Blancha teaches a software architecture that has a few attributes. First, it provides deterministic execution times. Second, it provides a method to enhance instrument software while preserving previous behaviors to assure back compatibility. Third, it provide a software layering approach that enables high level interfaces to be translated to different implementations of fixed instrument architectures. However, the tester instrument is still a legacy fixed instrument architecture that is cycle & time set based with no native links to the design environment.
U.S. Patent Application No. 2011-0202799 to Pagini: this describes a very specific front end extension to a legacy fixed architecture digital instrument to accomplish a couple of things. First, it enables channel fan in/out (few tester pins running at higher frequency are translated to more pins to the DUT running at a lower frequency). Second, it acts as an adapter/translator that enables multiple versions of legacy fixed instrument architectures to test the same device. This front end extension is quite limited in its reconfigurability to register lengths, depths, and communication IF back to the tester. The tester instrument is still a legacy fixed instrument architecture that is cycle & time set based with no native links to the design environment.
The current ATE systems largely utilize digital instruments that are based on the concept of a pattern generator. This pattern generator is a synchronous state machine that pumps out deterministic patterns—sequences of 1's & 0's—to the device and also compares the output of the device to expected data. This pattern generator has very limited algorithmic capability, as these systems were essentially designed for testing of earlier semi-conductor devices, dating back to the use of Intel's x86 processors, having wide synchronous addresses and data busses, and with it is programs in rows of 1's and 0's, where each row has the option of an “op code” which is an assembly code level instruction like a repeat, jump, etc.
Over time devices have evolved to have multiple, completely independent interfaces (USB, HMDI, SCSI, DDR, etc.). These interfaces are generally independent from one another, have complex handshaking algorithms, and can be non-deterministic in their behavior. This makes utilizing of the legacy fixed pattern generator architectures challenging. So, various enhancements in prior art inventions have been made to the pattern generator architecture to give it more flexibility and to try to run them faster, including partitioning them to have multiple pattern generators in a system. And per some of the following patents, like the Connor patents, the enhancements seek to put hooks in to handle the non-deterministic protocols.
U.S. Patent Application Publication No. 2011/0276302 by Rivoir, U.S. Patent Application Publication No. 2010/0313071 by Connor, and U.S. Pat. Nos. 8,269,520 and 8,195,419 to Connor describe an augmentation to a fixed legacy architecture system that would provide a subset of the functionality offered by the present invention. In their design, the existing fixed architecture is used to control the protocol state machine loaded into the FPGA. The Connor inventions address only non-deterministic use cases, and do not disclose implementing an entire and complete protocol specific instrument (disclosed hereinafter as IIP) within the FPGA. In addition these patents and patent application publications do not teach utilization of a common programming environment that spans pre-silicon simulation, post silicon validation, and production test, nor do they capture the non-digital use cases or the verification acceleration use cases.
In U.S. Pat. No. 8,268,520, Connor teaches a mode where there are two pattern generators, one for Tx and one for Rx, and these pattern generators can be coordinated, and can be implemented in FPGAs, which is fairly common today. The programming model is the same—rows of data and optional op codes.
In U.S. Pat. No. 8,195,419, Connor teaches enhancing the pattern generator state machine with circuits that enable the pattern generator to emulate some aspects of some protocols, but still being within the synchronous state machine architecture, and again, with the same programming enhanced with additional op codes that can be used for vector (row of 1's & 0's).
U.S. Patent Application Publication No. 2010/0313071 by Connor teaches using the pattern generator to control circuits that can “simulate” aspects of some protocols to handle non-deterministic modes of the device interface. So the pattern generator becomes more “protocol aware,” but with the same programming enhanced with additional op codes that can be used for vector (row of 1's & 0's).
U.S. Patent Application Publication No. 2010/0313089 by Rajski describes a method to transfer patterns from a fixed architecture instrument to the device for scan based structural test using high speed serial interfaces to reduce the number of tester channels required to send & receive the data, which is a highly specific augmentation limited to legacy instruments.
U.S. Patent Application Publication No. 2011/0148456 by Mooyman-Beck describes a method for connecting signal conditioning circuit to the device under test using multi-chip packaging (die-to-die) technologies, which again assumes a legacy architecture test system and simply provides for a new way to connect & condition the DUT pins to the legacy test system.
So in summary, none of the prior art disclosures teach or suggest utilizing tester instrument architecture that is entirely reconfigurable with Test IP natively linked with the design simulation/verification environment, and do not disclose and teach utilization of a common programming environment that spans pre-silicon simulation, post silicon validation, and production testing.